Growable packet switch architecture

ABSTRACT

This invention is large N×N packet switch, formed using a plurality of smaller packet switches. The invention comprises an N input, L output interconnect fabric (L&gt;N), and a plurality of J×K smaller packet switches (J&gt;K). Each of the J inputs to each packet switch is connected to a separate one of the L outputs of the interconnect fabric, and each of the K outputs from each packet switch is connected to a destination equipment. In operation, packets are received at the N inputs to the interconnect fabric, and each packet is routed to one of the inputs of the packet switch associated with the destination user equipment for the packet. Simultaneous packets, up to J in number, are routed to separate inputs of a particular packet switch for distribution to their respective destinations, while all other simultaneous packets destined for user equipments associated with the same packet switch are lost, the probability of such a loss being acceptably small.

Cross-reference to related application, U.S. patent application Ser. No.400,184 filed concurrently herewith.Iadd., now U.S. Pat. No.4,955,016.Iaddend..

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to packet switches and more particularlyto an arbitrarily large packet switch.

2. Description of the Prior Art

The internal components of packet switch often operate several timesfaster than the rate at which the packet switch receives or transmitspackets. This speed of operation is necessary to enable the packetswitch to route different packets, simultaneously received at multipleinputs, to the same output. However, such a high speed of operationrequires that the packet switch be implemented on a single integratedcircuit chip or a single circuit card, and thus, the number of inputsand outputs which a packet switch can comprise is limited by the numberof inputs and outputs which can be placed on a circuit chip or a circuitcard. One packet switch which overcomes the problem in some regard isdisclosed in U.S. Pat. No. 4,577,308, issued to Larson et al. on Mar.18, 1986. In this packet switch, several outputs are multiplexed by anon-chip multiplexer, and the multiplexed output signal is sent off thechip by means of a single output lead. Similarly, a multiplexed inputstream is received at a single input pin of the chip, and an on chipdemultiplexer demultiplexes the signal and supplies the separated inputsignals to separate inputs of the packet switch. Although this overcomessome of the difficulties of prior art devices, it requires on-chipmultiplexing/demultiplexing, and, therefore, the allowable size of thepacket switch is still limited. The problem that remains is to provide apacket switch which can be modularly grown as large as an expandingnetwork may require.

SUMMARY OF THE INVENTION

The foregoing problem in the prior art has been solved in accordancewith the present invention which relates to a packet switchingarrangement formed by interconnecting a plurality of J-input byK-output, small sized packet switches, designated output packetswitches, to separate outputs of an inventive N-input by L-outputinterconnect fabric, where N<L>J. The N×L interconnect fabric can acceptconcurrent packets at its N inputs from external sources and selectivelyforward such packets to separate ones of its L outputs. The L outputs ofthe interconnect fabric are grouped into predetermined subsets of Joutputs each, and each subset of J outputs is coupled to J inputs of aseparate one of the plurality of J×K output packet switches. Each of theK outputs of an output packet switch is arranged to transmit packetsreceived from the interconnect fabric to a different destinationequipment. In operation, packets each comprising an information fieldand a destination address, arrive at the interconnect fabric. Based uponits destination address, each packet is routed to any one of the inputsof the particular output packet switch which has the destinationequipment of the packet connected to one of its K outputs. If more thanJ packets destined for the same output packet switch arrivesimultaneously at the inputs to the interconnect fabric, all packets inexcess of J are lost, since each output packet switch only includes Jinputs and can, therefore, only accept a maximum of J simultaneouslyarriving packets. The probability of this loss however, is sufficientlysmall to be acceptable in practical systems. It should be obvious thatin cases where no excess packet dropping is allowed, additional bufferscan be provided to temporarily store these excess packets forretransmission.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an exemplary packet switchingarrangement in accordance with the present invention;

FIG. 2 shows a block diagram of an inventive interconnect fabric whichcan be used within the inventive packet switching arrangement of FIG. 1;

FIG. 3 shows a block diagram of a possible implementation of theinterconnect fabric of FIG. 2;

FIG. 4 shows portions of exemplary hardware for use in the interconnectfabric of FIG. 2; and

FIG. 5 shows further portions of exemplary hardware for use in theinterconnect fabric of FIG. 2.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of an exemplary implementation of a packetswitching arrangement according to the invention comprising (1) aninterconnect fabric 109 including (i) a plurality of 8 interconnectfabric inputs 101-108, and (ii) a plurality of 16 interconnect fabricoutputs 122-137, grouped into subsets of 4 interconnect fabric outputseach; i.e. interconnect fabric outputs 122-125, and (2) a plurality of 4output packet switches 110-113, each including (i) a plurality of 4output packet switch inputs, and (ii) a plurality of 2 switch outputs,i.e. switch outputs 114-115 of output packet switch 110. Each outputpacket switch is arranged to receive data packets from a separate subsetof the interconnect fabric outputs as shown in FIG. 1, and route suchpackets to either one of the two outputs which are connected to possiblyseparate end user devices.

In operation, packets arrive simultaneously, during predetermined timeslots, at interconnect fabric inputs 101-108 and are read intointerconnect fabric 109. Interconnect fabric 109 determines, from thedestination address in each packet, which subset of interconnect fabricoutputs 122-137; i.e. which output packet switch, each of the packets isdestined for, with several packets possibly being destined for the samesubset of outputs; i.e. subset 122-125 of FIG. 1. However, each packetis routed to a separate one of the interconnect fabric outputs 122-137.If several packets are destined for the same switch output, i.e. switchoutput 114, or, if several packets are destined for different switchoutputs of the same output packet switch, i.e. outputs 114 and 115 ofoutput packet switch 110, each of these packets is routed to a separateinput of that packet switch by means of a separate one of associatedsubset of interconnect fabric outputs 122-137. The interconnect fabric109 is considered novel in that previously known interconnect fabricswould examine the address in the arriving packet and uniquely map thataddress to a particular single output. Present interconnect fabric 109,however, maps the address in each packet to a subset of severalinterconnect fabric outputs, and then sends the packet to any availableoutput in that subset. (See copending U.S. patent application No.400,184 filed by the same inventors on the same day as this patentapplication).

Once the concurrent packets received at the interconnect fabric inputs101-108 during a particular time slot are routed through theinterconnect fabric and received by their respective output packetswitches 110-113, the interconnect fabric 109 is cleared and awaits thearrival of packets during the next time slot. Further, the output packetswitches are each responsible for routing the received packets to theirdestined switch outputs, i.e. 114-115 of output packet switch 110, basedupon the destination address in each packet, and in accordance with anystandard packet switching technique of the prior art. If more than fourpackets arrive simultaneously at interconnect fabric inputs 101-108which are destined for outputs of the same output packet switch, allthose in excess of four will be discarded by the interconnect fabricbecause, as shown in FIG. 1, each output packet switch can only accept amaximum of four simultaneous packets, one at each of its inputs. Themethod of determining which packets to discard will be discussed laterherein.

If packets arrive independently at interconnect inputs 101-108, theprobability of packet loss is given by: ##EQU1## where p is the loading;i.e. the probability that a packet arrives during a given slot at agiven interconnect fabric input. Further, it can be shown that as N→∞,the probability of packet loss becomes ##EQU2## For example, using a1000×1000 packet switch constructed with (1) fifty 50×20 output packetswitches, the 50×20 output packet switches being well within the sizethat is available with current technology, and (2) a 1000×2500,interconnect fabric, the packet loss probability is less than 10⁸,assuming that .[.p≦0.9.]. .Iadd.p≦0.9. .Iaddend.The packet lossprobability using the inventive packet switch is normally acceptable inmost practical systems, but can be adjusted in accordance with theparticular system requirements of the user and the above equations,which can easily be programmed into any computer to yield a solution.

FIG. 2 show a block diagram of an exemplary interconnect fabric 109 inaccordance with the invention, as well as the connection from theinventive interconnect fabric 109 to the output packet switches 110-113.The exemplary interconnect fabric 109 comprises four input modules201-204, each comprising (1) two interconnect fabric inputs, i.e. 101and 102 of input module 201, and (2) four input module outputs, i.e.209-212 of input module 201. The interconnect fabric 109 furthercomprises four intermediate modules 205-208, each arranged to receivedata packets from a separate output of each of input modules 201-204,and to transmit data to a separate output of interconnect fabric 109corresponding to a separate input of each of output packet switches110-113. For purposes of explanation, input module outputs 209-224 andoutput packet switch inputs 122-137 of FIG. 2 are collectively referredto herein as paths, since they are actually communications paths used tocommunicate packets from an input module to an output packet switch.Therefore, FIG. 2 comprises 32 paths, 16 first paths labeled 122-137 and16 second paths, labeled 209-224. The interconnect fabric 109 implementsan efficient routing algorithm for conveying the packets from the inputmodules 201-204 to the output packet switches 110-113 through the use ofthe intermediate modules 205-208 and paths 209-224 and 122-137, asdescribed hereinafter.

In operation of the routing algorithm, packets arrive simultaneously ina given time slot at the inputs 101-108 to the input modules 201-204.The time slot is broken down, internal to interconnect fabric 109, intoM minislots, where M is equal to the number of input modules, plus atransmission slot to be explained later herein. Hereafter, carefulattention should be given to the distinction between a time slot, duringwhich several simultaneous packets arrive at the inputs 101-108 ofinterconnect fabric 109, and minislots, M of which comprise a time slot.During the first minislot, a separate particular output packet switch isassigned to each input module. Each input module then examines thedestination address in each packet received during the time slot anddetermines which packets are destined for the particular output packetswitch assigned to the input module during that particular minislot. Forexample, during the first minislot, output packet switches 110-113 mightbe assigned to input modules 201-204, respectively. This would implythat during the first minislot, input module 201 would be examining itsreceived packets to determine which ones, if any, are destined foroutput packet switch 110, or equivalently, which packets of the possibletwo that were received at interconnect fabric inputs 101 and 102, ifany, are destined for switch outputs 114 or 115. Also during this firstminislot, input module 202 would be determining which packets of thosethat arrived at interconnect fabric inputs 103 and 104 during the timeslot are destined for output packet switch 111, or equivalently, whichpackets are destined for switch outputs 116 or 117. Input modules 203and 204 would function similarly for their respective received packetsand respective assigned output switches 112 and 113.

For each packet destined for the particular assigned output packetswitch, each input module would reserve one of its associated paths;e.g. path 209 of input module 201, and a path associated with theparticular output packet switch to which the packet is destined e.g.path 122 of output packet switch 110. Both reserved paths must beconnected to the same intermediate module; i.e. paths 122 and 209 areboth connected to the same intermediate module 205. The intermediatemodule is then responsible for providing a connection between the twopaths for conveyance of the packet from the input module to the outputpacket switch during a subsequent minislot provided for packettransmission. At the end of the first minislot, each input module wouldstore a small amount of data indicating which of its associated pathshad been reserved in the first minislot. A record would also be made atthe end of the first minislot, possibly at each output packet switch, ofwhich particular paths 122-137, connecting the interconnect fabric tothe four output packet switches, have been reserved.

During the next minislot of the same time slot, each output packetswitch is assigned to a new input module. For example, the secondminislot of the time slot could assign output packet switches 110, 111,112, and 113 to input modules 202, 203, 204, and 201, respectively. Eachoutput packet switch may have had some of its associated paths reservedfrom the first minislot, and the information as to which paths of anoutput packet switch have been previously reserved must be passed to theinput module which is currently assigned to the output packet switch.Each input module already will have its own information indicative ofwhich of its associated paths have previously been reserved, since eachinput module stores this information when it reserves one of itsassociated outputs. Thus, at the start of the second minislot, eachinput module will have (1) information indicative of which of its paths;e.g. 209-212 of input module 201, have been previously reserved, and (2)information indicative of which paths of the particular output packetswitch it is assigned to, have also been previously reserved; e.g. whichof paths 134-137 of output packet switch 113 were reserved by assignedinput module 204 during the first minislot.

During the second minislot, each input module examines the packetsreceived during the time slot, searching for packets that are destinedfor the new assigned output packet switch. For each packet found to bedestined for the particular assigned output packet switch, each inputmodule again reserves a set of paths, in a similar manner as before,with the added restraint that no previously reserved paths may bereused. At the end of the second minislot, the output packet switcheswill once again be reassigned, and the process will continue until eachof output packet switches 110-113 has been assigned to each of inputmodules 201-204. At the beginning of each minislot, each input modulewill always contain a cumulative record of which of its paths, i.e.paths 209-212 of input module 201, have been reserved during previousminislots. Further, each input module will be passed a cumulative recordof which paths of the output packet switch currently assigned to theinput module have also been previously reserved by other input modulesduring previous minislots. At the conclusion of the fourth minislot, atransmission slot, briefly mentioned above, is reserved for transmissionof the packets through interconnect fabric 109 via the previouslyreserved paths and for resetting the interconnect fabric to receive anew set of simultaneous packets during the next time slot.

Note that once an output path of an input module is reserved for apacket, this reservation, and an indicator of which minislot the systemis in, will uniquely determine which of the output packet switch paths122-137 must be reserved and the proper connection which must be madethrough the intermediate module. For example, and referring to FIG. 2,if input module 201 reserves path 209 during the first minislot,intermediate module 205 must connect path 209 to path 122. This isbecause during the first minislot, input module 201 is assigned tooutput packet switch 110. Therefore, it follows that if path 209 isreserved during the first minislot, it must be for conveyance of apacket to output packet switch 110 through intermediate module 205. Butas FIG. 2 shows, path 122 is the only path to transmit data fromintermediate module 205 to output packet switch 110. Therefore, thereservation of path 209 during the first minislot uniquely determinesthe connection which must be made at intermediate module 205. Thisconcept can be extended to the case where multiple paths which areconnected to the same intermediate module are reserved during aminislot. For example, if input module 201 reserved path 209 during thefirst minislot while input module 202 reserved path 213 during the firstminislot, intermediate module 205 would connect paths 209 and 213 topaths 122 and 126, respectively. This is because the pairs of paths209-122 and 213-126 form connections from input module 201 to outputpacket switch 110 and from input module 202 to output packet switch 111,respectively. Intermediate module 205 would know that the connectionpairs 209-126 and 213-122 would be incorrect. This is because paths209-126 would correspond to a connection from input module 201 to outputpacket switch 111, and paths 213-122 would correspond to a connectionbetween input module 202 and output packet switch 110, both connectionsbeing inconsistent with the input module/output packet switchassignments for the first minislot. However, if during a futureminislot, input modules 201 and 202 were assigned to output packetswitches 111 and 110, respectively, and paths 209 and 213 were availableand reserved during this future minislot, the connections 209-126 and213-122, different from those above and corresponding to the differentinput module/output packet switch assignments than those discussedabove, would be the correct connections. An exemplary circuit for doingthis selective switching is detailed later herein.

One exemplary way to implement the described routing method, not to beconstrued as limiting the scope of the invention, is to have one or moresmall processors, possibly microprocessors, in the interconnect fabric109, and reserve a four bit block of memory both for each of the inputmodules 201-204, and for each of the output packet switches 110--113. Ablock diagram of a portion of this exemplary implementation is shown inFIG. 3. Each of the memory blocks of FIG. 3 is labeled mxxx, where xxxis the input module or output packet switch to which the memory blockcorresponds. For example, m201 of FIG. 3 is the memory block whichcorresponds to input module 201 of FIG. 2. Each bit in each memory blockrepresents a separate one of the communications paths from FIG. 2, andeach bit of the memory blocks m110-m113 and m201-m204 of FIG. 3 islabeled to correspond to the communications path which it represents.Each input module comprises two input buffers, i.e. input buffers I101and I102 of input module 201, to be used to buffer the arriving packetsat the beginning of a time slot. Further, each input module comprisesfour output buffers, i.e. O209-O212 of input module 201. Each outputbuffer O209-O224 corresponds to a separate one of communications paths209-224. The intermediate modules 205-208 are each arranged to monitorthe status of any of the bits b209-b224 of memory blocks m201-m204 whichcorrespond to paths that terminate at the intermediate module. Forexample, intermediate module 205 is arranged to monitor the status ofbits b209, b213, b217, and b221, since, as FIG. 2 shows, the pathscorresponding to these bits are all connected to intermediate module205. These monitoring connections are not shown in FIG. 3 for clarity.

At the start of a time slot, simultaneous packets arrive at interconnectinputs 101-108 and are read into input buffers I101-I108 of FIG. 3,respectively. Each input module is assigned a separate output packetswitch 110-113 for the duration of the first minislot, and is thusarranged to read from, and write to, the proper one of memory blocksm110-m113 corresponding to the particular output packet switch assignedto the input module. If any of the packets in the input buffers of anexemplary input module are destined for the particular output packetswitch assigned to that input module, the input module reserves a set ofpaths by complementing the corresponding bits of the appropriate memoryblocks m201-m204 and m110-m113 of FIG. 3. The intermediate modules205-208 then interpret the bits and connect the proper paths. Forexample, if input module 201 reserves paths 209 and 122 during anexemplary minislot, input module 201 would complement bits b209 and b122in FIG. 3. Intermediate module 205, which monitors bit b209, woulddetect that it has been complemented during the minislot and would,therefore, connect paths 209 and 122 to each other. After reserving thepaths by complementing the bits, the input module 201-204 places thepacket to be transmitted over the reserved paths into the correspondingone of the output buffers O209-O224 of FIG. 3. As the packets are placedinto output buffers O209-O224 during successive minislots of a timeslot, there are fewer packets remaining in the input buffers, and thereare fewer packets to examine during each successive minislot.

At the end of the first minislot, each input module is assigned a newoutput packet switch. This could be accomplished physically byimplementing the memory blocks m110-m113 of FIG. 3 as a 16 bit shiftregister, and then cyclically shifting the shift register by four bitsin either direction. After the shift, each input module 201-204 would bearranged to monitor the four bits previously monitored by a differentinput module. Further, each set of four bits b122-b125, b126-b129,b130-b133, and b134-b137, will have the reservations, i.e. complementedbits, from the previous input module(s) to which it was assigned. Thus,this shift register cyclic rotation provides a method to supply eachinput module with a cumulative record of which paths of the currentlyassigned output packet switch have been previously reserved by inputmodules to which the currently assigned output packet switch waspreviously assigned. The shift register approach could also be replaced,for example, with a computer bus. Referring to FIG. 3, all sixteen bitsb122-b137 could be bussed to each of the input modules 201-204, and eachinput module could monitor a separate four bits during any minislot.When a new minislot begins, each input module 201-204 would switch overand monitor a different set of four bits chosen from b122-b137,corresponding to a different output packet switch assignment. Each inputmodule can now continue reserving paths during each minislot bycomplementing bits. If too many packets arrive which are destined for aparticular output packet switch, the interconnect fabric will run out ofavailable paths to that output packet switch during a time slot. Afterthe supply of paths is depleted, all other packets destined for thatoutput packet switch during that time slot will be discarded. At theconclusion of the fourth minislot, the packets are conveyed to theoutput packet switches via the previously reserved paths during thetransmission slot, all the memory blocks are reset to their inactivestate, and the interconnect fabric is ready to accept packets in thenext time slot.

A slight inefficiency exists in the routing algorithm which should benoted. As described above, when an input module output and an outputpacket switch input are reserved for a packet, both must be connected tothe same intermediate module. This translates into a very specificrequirement on the exemplary memory block implementation of FIG. 3. Moreparticularly, it means that the bit position reserved in the memoryblock m201-m204 corresponding to the input module must be the same asthe bit position reserved in the memory block m110-m113 corresponding tothe currently assigned output packet switch. For example, to convey anexemplary packet from input module 201 to output packet switch 110, anyof the bit pairs b209-b122, b210-b123, b211-b124, or b212-125 of FIG. 3would suffice, assuming that none of the corresponding paths have beenpreviously reserved. Note that b209 and b122 are both in the firstposition of their respective memory blocks m201 and m110. Similarly,b210 and b123 are both in the second position of their respective memoryblocks m201 and m110. The other bit pairs discussed above have the sameproperty. Because of this requirement, it is possible that for a giveninput module/output packet switch assignment during a particularminislot, several paths could be available from the input module andseveral paths could be available to the output packet switch but packetsbetween the two are still lost. This situation would occur if none ofthe paths available from the input module are connected to the sameintermediate module as the available output packet switch paths areconnected to. For example, and referring to FIG. 2, suppose during thethird minislot input module 201 is assigned to output packet switch 112.Further assume that during previous minislots paths 209 and 131-133,among others, have been reserved for transmission of packets through theinterconnect fabric. FIG. 2 shows that although output packet switch 112still has an associated path 130 available i.e. not previously reserved,and further, input module 201 still has paths 210 through 212 available,no connection can be made through the interconnect fabric of FIG. 2 frominput module 201 to output packet switch 112 because the available path130 of output packet switch 112 is not connected to the intermediatemodule as any of the available paths 210-212 of input module 201. Thispacket loss probability is in addition to the packet loss probabilityyielded by the previous equation (1) and (2), which is due to more thatfour packets arriving at the interconnect fabric inputs 101-108 whichare destined for the same output packet switch. However, even with thisextra packet loss probability, the probability that a packet will not belost is approximately 98% to 99% of the number given by the aboveequations, and is therefore still acceptable in most practical systems.

A block diagram of a portion of an exemplary logic circuit forimplementing the functions of exemplary intermediate module 205 is shownin FIG. 4. It is to be understood that FIG. 4 shows only the portion oflogic circuitry required to implement the first minislot within eachintermediate module. Further, FIG. 4 is shown only for illustrativepurposes, and is not to be construed as limiting the scope of theinvention. A Demultiplexer 400 interprets the system clock, or aminislot indicator timing signal supplied by the system clock, andselectively sets active one of the output lines 405-408 which is enabledto indicate the proper minislot. For example, during the first minislot,line 405 goes active, enabling logic gates 401-404. If any one or moreof the bits b209, b213, b217, or b221 have been set active by an inputmodule, the corresponding output 414-417 from pulse generator 413 willgenerate a one minislot wide pulse, and the output from thecorresponding logic gate 401-404 will be activated. This activatedoutput will then enable the proper one or more latched switches 409-412,by setting active the input E of the latched switches 409-412. Theoutputs from logic gates 401-404 are connected to latched switches412-409, respectively. This activation of the E bit on any one or moreof latched switches 409-412 will cause the input of the latched switchto be connected to the corresponding output 122, 126, 130, or 134,providing the connection between the two paths originally reserved bythe input module. This connection will remain as set by the logic forthe entire time slot, so that the packets can all be conveyed throughthe interconnect fabric at the end of the time slot. Not shown are thereset inputs to the latched switches 409-412, used for resetting thelatched switches after transmission of the packets through theinterconnect fabric at the end of the time slot.

For operation during each of the remaining three minislots, a set ofgates analogous to gates 401-404 would be utilized. FIG. 5 shows asecond portion of the exemplary circuit of intermediate module 205, thissecond portion being for possible use during a second minislot. Notethat demultiplexer output 406 of FIG. 5 is asserted active during thesecond minislot, enabling a different set of gates 501-504 instead ofthe set 401-404 enabled during the first minislot. Further, note thatinputs and outputs to latched switches 409-412 of FIG. 4 are pairedtogether differently than the inputs and outputs to latches switches509-512, of FIG. 5 corresponding to the different input module/outputpacket switch assignments. FIG. 5 shows that if a bit b209, b213, b217,or b221 goes active during the second minislot, gates 501-504 willcomplete the corresponding connection from paths 209-134, 213-122,217-126 or 221-130, through the proper one of switches 509-512. Notethat once a bit b209, b213, b217, or b221 is set active, and theminislot signal is provided, the circuitry of FIGS. 4 and 5 can providethe proper connections through the intermediate module. As wasemphasized previously, once the input module path is selected and theminislot is known, this determines the output packet switch path whichmust also be reserved.

A different strategy for implementing the connections through theintermediate modules 205-208 is based upon self routing the packetsduring each time slot rather than establishing connections through theintermediate modules 205-208 as described in FIGS. 4 and 5. Referring toFIG. 3, in the self routing method, after activating the proper bits toreserve the required paths, each input module would place the packets inthe output buffers O209-O224 as described above. However, in theself-routing method, no switches within the intermediate module exist.Rather, each packet contains a field of one or more bits, denoted hereinas the "route" field, which the input module 201-204 sets, and whichspecifies the particular one of paths 122-137 of FIG. 2 to which theintermediate module should route the packet to. At the end of theminislots, the packets are transmitted to the intermediate modules,which interpret the route field and transmit the packets over the properone of paths 122-137 as specified in the route field of each packet.

It is to be understood that the exemplary circuitry shown in each ofFIGS. 4 and 5 is not to be construed as limiting the spirit or scope ofthe invention. The entire intermediate module could be implemented asany combination of hardware and software, or with other hardwarearrangements than those of FIG. 4 or 5 which can be easily constructedby anyone of ordinary skill in the art. The entire set of intermediatemodules 205-208 could be replaced by a smaller number of largerintermediate modules, say two 8×8 modules, rather that the four 4×4intermediate modules shown. The memory blocks m201-m204 could beeliminated, and the input modules 201-204 could examine their own outputbuffers O209-O224 to determine which paths 209-224 have been previouslyreserved. More particularly, if path 219 were reserved by input module203, for example, the packet to be transmitted over the path would beloaded into output buffer O219 as described above. Therefore, in afuture minislot, rather than check to see if b219 were set as waspreviously described, input module 203 could just check its outputbuffer O219 of FIG. 3 and if the buffer is loaded, it would indicatethat path 219 has been previously reserved.

Still further embodiments of the invention are possible and easilyimplementable by anyone of ordinary skill in the art. The interconnectfabric 109 could begin routing the packets at the end of each minislot,rather than waiting until the end of the entire time slot. The inputmodules could begin accepting a new set of packets while transmittingthe set from the previous time slot. The number of inputs J to eachoutput packet switch 110--113 or the number of outputs from each inputmodule 201-204 need not be the same. Further, one or more of the outputpacket switches may only have one input. If it is known in advance thatmuch of the traffic is destined for a particular output packet switch,for example, this output packet switch could have more inputs than therest of the output packet switches. There also need not be the samenumber of input modules as output packet switches, and the intermediatemodules could have different numbers of inputs and outputs from eachother. Further, one or more intermediate modules could be arranged foruse by only specified input modules, rather than all of the inputmodules, thereby permitting higher priority for packets arriving atthese specified input modules.

The interconnect fabric can be generalized even more to handle a mix ofpacket and circuit traffic. Suppose we desire to provide a circuitconnection from an arbitrary interconnect fabric input, say 101, to anyinterconnect fabric output of an arbitrary group of interconnect fabricoutputs, say 122-125 of FIG. 1, for transmission of a digital bitstream. The interconnect fabric could, at the beginning of each timeslot, reserve a path from interconnect fabric input 101 to interconnectfabric output 122, for example, before the reservation algorithmdescribed herein begins to reserve paths. Thus, during each time slot, aset of paths connecting interconnect input 101 to interconnect fabricoutput 122, for example, paths 210 and 123 of FIG. 2, would be offlimits to the reservation algorithm, and would be reserved for circuittraffic. Any block of data which arrived at interconnect fabric input101 during the time slot would be sent to interconnect fabric output122, without examining an address within the block of data. If therequired speed of the circuit connection were lower than the rate atwhich the interconnect fabric accepts packets, say one third as fast,than the block of data arriving during every third time slot could beprocessed as circuit traffic, while the two in between time slots wouldbe available for normal data packets. Furthermore, the block of data,being part of a bit stream to be transmitted over a circuit connection,may not even contain an address.

These blocks of data are designated herein as exception data packets,and are to be understood to be encompassed by the term data packet. Theonly differences between the processing of these exception data packetsand the data packets previously described above is: (1) that the mappingdiscussed herein is based upon the time slot during which the exceptionpacket arrives and the interconnect fabric input at which the exceptionpacket arrived, rather than an address in the packet, and (2) theexception packets may be routed to a single output rather than a groupof outputs. Finally, a plurality of inputs 101-108, during various timeslots, could be reserved for transmission of these blocks of data. Thissimply means that during predetermined time slots, predetermined ones ofbits b209-b224 and b122-b137 would be complimented at the beginning ofthe time slot, and thus off limits to all normal data packets.

The lost packet probability can be made even smaller by the use of extrabuffering within the interconnect fabric. More particularly, rather thandiscard all packets for which there are no available paths during a timeslot, one could buffer the excess packets until a subsequent time slot,when paths from the input module at which the packets were received tothe destination output packet switch for the buffered packets becomeavailable. This method however, may not be cost effective because theprobability of packet loss can be made so small without the extrabuffering, that the cost of saving one lost packet per ten billion, forexample, may not justify the extra storage and processing required tosave the packet rather than just discard it.

We claim: .[.1. A packet switching arrangement comprising:communications path for each data packet..]. .Iadd.4. A packet switchingarrangement comprising:(i) an interconnect fabric comprising, aplurality of input ports for receiving data packets, a plurality ofgroups of output ports, each group comprising a separate number of oneor more output ports, each of said output ports for supplying datapackets as an output and each output port of a particular group beingassigned to a common destination which is different from a destinationassigned to output ports of at least another group, where the separatenumber of output ports comprised in a group of output ports may be thesame as or different from the number of output ports comprised in othergroups of output ports, at least one of the groups comprising more thanone output port, and means for mapping each received data packet to agroup of output ports and for mapping concurrently received data packetsdestined for a particular one of said destinations to respective outputports in a particular group assigned to the particular destination, saidmeans for mapping including means for establishing a separatecommunications path from each separate input port at which each datapacket is received to a separate output port of the group of outputports to which the data packet is mapped and for transmitting each datapacket over the separate established communications path, (a) aplurality of input modules, each input module comprising (1) at leastone input, each input being coupled to a separate interconnect fabricinput port, (2) a plurality of outputs and (3) means for selectivelyconnecting any input to any output for forming a first portion of theestablished communications path for each data packet, (b) a plurality ofintermediate modules, each intermediate module comprising (1) aplurality of inputs, each input is coupled to a separate input moduleoutput, (2) a plurality of outputs, each output being coupled to aseparate interconnect fabric output port of a predetermined number ofgroups of interconnect fabric output ports, and (3) means forselectively connecting any intermediate module input to any intermediatemodule output for forming a second portion of the establishedcommunications path for each data packet; and (ii) a plurality of outputpackets switches, each output packet switch being arranged to receivedata packets from a separate group of interconnect fabric output portsand route the data packets to one or more destinations..Iaddend..Iadd.5. A packet switching arrangement as defined in claim 4 whereinsaid plurality of interconnect fabric input ports includes a firstnumber of of input ports and said plurality of interconnect fabricoutput ports includes a second number of output ports larger than saidfirst number of input ports..Iaddend. .Iadd.6. A packet switchingarrangement as defined in claim 5 wherein said data packets aretransported through said interconnect fabric on a circuit switchedbasis..Iaddend. .Iadd.7. A packet switching arrangement as defined inclaim 5 wherein each of said plurality of packet switches includes aplurality of input ports and a plurality of output ports..Iaddend..Iadd.8. A packet switching arrangement as defined in claim 7 whereinsaid plurality of packet switch input ports includes a third number ofinput ports and said plurality of packet switch output ports includes afourth number of output ports fewer than said third number of inputports..Iaddend. .Iadd.9. A packet switching arrangement as defined inclaim 4 wherein said interconnect fabric further includes means fordiscarding those data packets received during a current time slot and inexcess of the separate number of output ports comprised in a particulargroup of output ports for which those excessive packets aredestined..Iaddend. .Iadd.10. A packet switching arrangement as definedin claim 4 wherein said interconnect fabric further includes means forstoring until a subsequent time slot, those data packets received duringsaid current time slot and in excess of the separate number of outputports comprised in a particular group of output ports for which thoseexcessive packets are destined..Iaddend. .Iadd.11. A packet switchingarrangement comprising:(i) an interconnect fabric comprising, aplurality of input ports for receiving data packets, a plurality ofgroups of output ports, each group comprising a separate number of oneor more output ports, each of said output ports for supplying datapackets as an output and each output port of a particular group beingassigned to a common destination which is different from a destinationassigned to output ports of at least another group, where the separatenumber of output ports comprised in a group of output ports may be thesame as or different from the number of output ports comprised in othergroups of output ports, at least one of the groups comprising more thanone output port, and means for mapping each received data packet to agroup of output ports and for mapping concurrently received data packetsdestined for a particular one of said destinations to respective outputports in a particular group assigned to the particular destination, saidmeans for mapping including means for establishing a separatecommunications path from each separate input port at which each datapacket is received to a separate output of the group of output ports towhich the data packet is mapped and for transmitting each data packetover the separate established communications path, said means forestablishing and for transmitting including (a) a plurality of inputmodules, each input module comprising (1) at least one input, each inputbeing coupled to a separate interconnect fabric input port, (2) aplurality of outputs, and (3) means for selectively connecting any inputto any output for forming a first portion of the establishedcommunications path for each data packet, and (b) a plurality ofintermediate modules, each intermediate module comprising (1) aplurality of inputs, where each input is coupled to a separate inputmodule output, (2) a plurality of outputs, each output being coupled toa separate interconnect fabric output port of a predetermined number ofgroups of interconnect fabric outputs and (3) means for selectivelyconnecting any intermediate module input to any intermediate moduleoutput for forming a second portion of the established communicationspath for each data packet; and (ii) a plurality of output packetsswitches, each output packet switch being arranged to receive datapackets from a separate group of interconnect fabric output ports androute the data packets to one or more destinations..Iaddend.